1. Field of the Invention
The present invention relates to laying out of wiring for electrical devices such as semiconductors where electrical elements such as semiconductor elements are mounted on an upper surface of a substrate and a plurality of connectors for connecting with an external substrate are formed on a lower surface of a substrate.
2. Description of Related Art
In recent years, packages equipped with various package structures have been put forward in accompaniment to high-density packaging of electronic equipment such as semiconductor devices, etc.
This kind of technology is disclosed in, for example, U.S. Pat. No. 5,216278 registered on Jun. 1, 1993, Japanese Patent Laid-open Publication No. Hei. 7-302858 laid-open on Nov. 14, 1995, Japanese Patent Laid-open Publication No. Hei. 9-22977 laid-open on Jan. 21, 1997 and Japanese Patent Laid-open Publication No. Hei. 9-223861 laid-open on Aug. 26, 1997.
In addition to where a single semiconductor device and an external device are used in combination, this kind of semiconductor device also has applications where a plurality of semiconductor devices having the same function are mounted on an external substrate and used as a single electronic device.
For example, a plurality of Dynamic Random Access Memory (DRAM) mounted on a Single In-line Memory Module (SIMM) or Dual In-line Memory Module (DIMM) or a plurality of LCD drivers mounted on an LCD driver substrate are well known.
When a plurality of semiconductor devices, where electrical elements such as semiconductor elements are mounted on an upper surface of a substrate and a plurality of connectors for electrically connecting with an external substrate are formed on the lower surface of this substrate, are mounted on an external substrate, the following problems occur.
When semiconductor devices X and Y having the same functions are mounted on the external substrate 200 as shown in FIG. 2, the distance traversed by wiring 202 across a terminal x1 for outputting a signal for the semiconductor device X and an output terminal 201 of the external substrate 200 and the distance traversed by wiring 202 across a terminal y1 outputting a signal of the semiconductor device Y and an output terminal 201 is substantially different. This is also the case when the semiconductor device Y is rotated by 180 degrees as shown in FIG. 3.
The terminals x1 and x2 are arranged at the lower surface of the semiconductors X and Y and in reality these terminals cannot be viewed from above. However, these terminals are expressed schematically in the drawings as dotted lines for ease of understanding.
This difference in distance becomes a much more serious problem as the semiconductor device is operated at higher speeds. Namely, time for transmitting signals from the semiconductor X to the external terminal 201 and the time for transmitting signals from the semiconductor Y to the external terminal 201 is different, and the timing of signals appearing at the external terminal 201 becomes different.
This also influences the operating speed of the whole of the electrical equipment on which the external substrate is mounted and makes design of the electrical equipment and setting of timing extremely difficult.
For example, if a personal computer, etc., mounted with SIMMs is assumed, this can easily be understood.
The use of two types of substrates having linearly symmetrical relationships has been considered for resolving this point. However, operating speeds between semiconductor devices become different because the length of the wiring connecting the substrate and the semiconductor elements is different within each semiconductor device.
Further, in addition to these two types of substrates, the use of two types of semiconductor elements having a linearly symmetrical relationship has also been considered. The use of this kind of configuration means that electrical characteristics of both devices can be considered to be the same but also means prohibitive increases in costs.
When a large number of like terminals of each semiconductor are connected using respective wiring, if laying out for each item of wiring is simply carried out, there is the possibility that intersections and short circuits may occur between wiring. Arrangements where each length of wiring is made to take a convoluted path in order to prevent intersections and short circuits have also been considered but this arrangement causes each length of wiring to become longer.